EDN

Verific Design Automation’s Netlist Only Parser, Database

Verific Design Automation, best known for its Verilog, SystemVerilog and VHDL parsers and elaborators, today said that its Netlist Only Parser is gaining momentum among electronic design automation ...
EDN

Verific’s Netlist-Only Parser Used in Achronix CAD Environment

Verific Design Automation today announced that Achronix Semiconductor Corporation, developer of the world’s fastest field programmable gate array (FPGA) called Speedster, uses Verific’s Netlist-Only ...
Design-Reuse

A Digital Design Flow for Differential ECL High Speed Applications

This paper presents a digital design flow in order to design high performance differential Emitter Coupled Logic (ECL) circuits efficiently. The proposed flow is similar to the ordinary digital CMOS ...
Semiconductor Engineering

Leveraging Symbolic Simulations For IO Verification

IO libraries and interface IPs are an important part of any integrated circuit design that needs to communicate with the outside world or other integrated circuits. Interface IPs are the literal ...
Design-Reuse

Domain Technologies announces Synthesizable MRAM8051 Microcontroller Netlist Library for Actel FPGAs Including Royalty-Free License for use in Tekmos Merged ASICs

Plano, Texas , October 12, 2006 - Domain Technologies announces the availability of the industry's first, royalty-free, synthesizable MCS8051 code-compatible microcontroller netlist library and ...