EDN

SpringSoft turns the power of Verdi on SystemVerilog test benches

SystemVerilog was supposed to be such a boon to verification engineers. By providing a Verilog-like language with extensions that made it easy to write transactors, assertions, and checkers, the ...
Electronic Design

SystemVerilog: The Complete Solution

The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips. With the IEEE-Std 1800-2005 System-Verilog standard, the industry has a ...
Hackaday

FPGA Testbenches Made Easier

You finally finish writing the Verilog for that amazing new DSP function that will revolutionize human society and make you rich. Does it work? Your first instinct, of course, is to blow it into your ...
Design-Reuse

Silicon Interfaces announces the release of its Open Verification Methodology (OVM) Based Gigabit Ethernet MAC SystemVerilog OVC

CAMPBELL, Calif., October 16, 2008-- Silicon Interfaces, a high-end design services and leading provider for IPs in Europe, North America and Asia-Pacific, announces the availability of their Gigabit ...
EDN

Synopsys claims first complete SystemVerilog flow

SAN FRANCISCO — Top-tier EDA vendor Synopsys Inc. Monday (March 20) laid claim to being the first EDA vendor to provide a complete SystemVerilog flow, saying the language is now supported throughout ...
Electronic Design

Tool Automates Generation Of SystemVerilog Testbenches

The SystemVerilog infrastructure is built out further with Synopsys' introduction of Pioneer-NTB. This testbenchautomation tool delivers native SystemVerilog testbench generation to users of ...