EDN

Resets in FPGA & ASIC control and data paths

Reset is an important mechanism to bring a digital system into a known state. The need for reset is governed by the system design and application, and various data and control paths are designed to ...
Embedded

Asynchronous reset synchronization and distribution – Special cases

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...
Embedded

Asynchronous reset synchronization and distribution – ASICs and FPGAs

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...
EDN

Efficient analysis of CDC violations in a million gate SoC, part 2

One interesting topic of discussion is whether to use synchronous or asynchronous reset in design. In synchronous reset design, we use reset signal in the D path of flop. Hence, the assertion of reset ...
Semiconductor Engineering

Reset Domain Crossing Verification

To meet low-power and high-performance requirements, system on chip (SoC) designs are equipped with several asynchronous and soft reset signals. These reset signals help to safeguard software and ...
Design-Reuse

Reset connectivity checks in complex low power architectures

Deepak Mahajan, Saloni Raina, Khushboo Gupta (Freescale Semiconductor, India Pvt Ltd.) With the growing advancement in semiconductor technology, there has been a drift towards the requirement of power ...