EDN

Static checker completes SystemVerilog support

The EZVerify static analysis tool from VeriEZ Solutions now addresses the complete SystemVerilog language, according to the company. The tool aims to help design and verification engineers create ...
EDN

Static and dynamic modeling for high-density memories

As designs increase in complexity, the density of memories that they connect to has also increased. It is not uncommon to see gigabyte memories. Having large memories comes with its own set of ...
Design-Reuse

Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs

Henderson, NV – February 6, 2023 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has updated its popular linting tool ALINT-PRO ...
Design-Reuse

Easier UVM Sequences - SystemVerilog UVM Sequence and Task Equivalence

SystemVerilog [1] UVM [2] sequences [4][5] are a powerful way to model stimulus and response for functional verification. Unfortunately using SystemVerilog UVM sequences can require an extensive ...