San Mateo, Calif. – A consortium of system-on-chip, intellectual-property and Universal Serial Bus physical-layer chip vendors has released an interface specification that it hopes will reverse the ...
BANGKOK, May 29, 2019 /PRNewswire/ -- As the industrial computing industry transitions from Low Pin Count (LPC) to enhanced Serial Peripheral Interface (eSPI) bus technology, developers face high ...
Sunnyvale, Calif. — Silicon Image, Inc. has introduced its Mobile High-Definition Link (MHL) technology at the Consumer Electronics Show (CES), which enables mobile phones, digital cameras, media ...
Macronix, the world-leading non-volatile memory (NVM) solution manufacturer, today unveiled its new-generation 12 pin-count bus interface called OctaBus. This breakthrough design delivers the high ...
Compensating for poor cable retention associated with low-pin count FPC connectors, the 6298 series FPC connectors employ a front-hinged actuator whereby the connectors lock the flex cable into ...
CHANDLER, Ariz., Sept. 26, 2023 (GLOBE NEWSWIRE) -- With the step-function increase in data collected and transmitted from cloud-connected edge nodes, Improved Inter Integrated Circuit ® (I3C ®) is ...
USB-to-serial interface chips are contained in a 3 x 3 mm 12-pin DFN packag. The UART interface IC allows asynchronous serial data transfer, supporting data transfer rates from 300 bits/s to 3 Mbits/s ...
Supported by a number of different interfaces and standards, flash memory can be custom-designed for a variety of applications. Earlier designs mostly adopted the parallel bus architecture. However, ...
SAN JOSE, Calif — A group of USB developers, including Philips and ARC International, are hammering out a board-level interface between USB controllers and physical layer (PHY) chips. The so-called ...
Results that may be inaccessible to you are currently showing.
Hide inaccessible results