For this year’s 7400 logic competition, [Nick] decided to build an FPGA out of logic chips (Internet Archive cached version). Perhaps a short explanation is in order to fully appreciate [Nick]’s work.

A recent trend has been to convert high-level constructs into FPGA code like Verilog or VHDL. Silice goes the other way: it converts very hardware-specific concepts to Verilog and aims to be a more ...

In this paper, the authors propose a compact AES (Advanced Encryption Standard) algorithm to achieve less slice consumption of FPGA. Proposed design is based on iterative round looping architecture. S ...