EDN

FPGA-Based FIR Filters using Distributed Arithmetic

M. Martinez-Peir, R. Colom, F. Ballester, and R. Gadea are teachers with a focus on digital applications at the Technical University of Valencia, Spain. They are currently working on video compression ...
EDN

PCI digitizer boards get FPGA-based FIR filters

Montreal, Canada—Digitizer maker Gage Applied Technologies is debuting FIR (finite impulse response) filters in FPGAs (field programmable gate arrays) in its line of 14-bit digitizers. The FIR filters ...
Electronics Weekly

DSP versus FPGA

In considering the design option for DSP vs. FPGA it is helpful to compare both architectures in a FIR filter application, writes Reg Zatrepalek One of the most widely used digital signal-processing ...
Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...
TechRepublic

FIR Filter Designing using Xilinx System Generator

Digital signal processing techniques are used extensively in a number of applications such as communication and multimedia. DSP functions such as FIR filters and transforms have numerous advantages ...
Design-Reuse

Optimizing Up/Down Conversion with FPGA Techniques

Digital upconverters (DUCs) and digital downconverters (DDCs) are important components of every modern wireless base station design. While many DUC and DDC designs are available, there is a clear call ...
Hackaday

FIR filter

Digital filters are always an interesting topic, and they are especially attractive with FPGAs. [Pabolo] has been working with them in a series of blog posts. The latest covers an 8th order FIR filter ...