EDN

Improved comparators distinguish between A = B = 0 and A = B = 1 states to enable better designs

Traditional digital comparator ICs are electronic analogs of mechanical lever scales. Like their mechanical counterparts, they compare two logical signals and produce an output (typically a voltage ...
EDN

Comparator-based buffer using a VVCCS

Editor’s note: PhD candidate, Seyyed Hossein Pishgar approached me with this paper, which I believe has some unique and creative circuitry and architectures. I have ...
Electronic Design

Comparators Drive 1.8V Logic Beyond 280MHz

Linear Technology Corporation announces the LTC6752 family of comparators with fast rise and fall times of 1.2ns and a toggle frequency of 280MHz, making them the fastest CMOS output comparators ...
Design-Reuse

Power input 3.3V, Comparator , UMC 55nm uLP/HVT Low-K Logic Process Ultra High Density (6T) C60 Core Cell Library

Power input 3.3V, Comparator , UMC 55nm uLP/HVT Low-K Logic Process Ultra High Density (6T) C60 Core Cell Library ...
Embedded

Leveraging FPGA and CPLD digital logic to implement analog to digital converters

Designers of digital systems are familiar with implementing the 'leftovers' of their digital design by using FPGAs and CPLDs to glue together various processors, memories, and standard function ...
CU Boulder News & Events

ECEA 5361 Hardware Description Languages for FPGA Design

This course will give you the foundation for using Hardware Description Languages, specifically VHDL and Verilog for Logic Design. You will learn the history of both VHDL and Verilog and how to use ...